Forum Discussion
Occasional ContributorHow to simulate a design created in Platform Designer System
Hi,
The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.
Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.
Thanks,
Best Regards,
Sheng
Super ContributorHi,
1) Setting counter_fifo.qsys file as top-level entity should be enough. ../Counter_FIFO/counter_fifo/sim and ../Counter_FIFO/counter_fifo/synth contain the same auto-generated .sv file so I think you can treat that .sv file in ../Counter_FIFO/counter_fifo/sim as top-level module. The Top-level HDL file of the design had been auto-generated.
2) Yup, .sv file in Project Folder/Qsys_system_name/synth will have the similar role of PLL_RAM.v in the example design. But since you're going to run simulation, have to use the .sv file in Project Folder/Qsys_system_name/sim.
Attached the zip file below. Check the do file sim.do in ../Counter_FIFO/counter_fifo/sim/mentor and example testbench counter_fifo_tb.v in ../Counter_FIFO/counter_fifo/sim. In do file, need to source the setup script msim_setup.tcl in sim/mentor then vlog both the top-level module counter_fifo.sv and example testbench counter_fifo_tb.v. Run the macro do file, you'll get the waveform like the picture attached below.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorHi,
Thank you very much for helping me out. I have a couple of questions.
As I have simulated my counter.v and with the testbench (please refer Counter_FIFO/counter_tb.v). The screenshot of the simulation wave I got is attached Capture.PNG.
I am just wondering that why I could not get the same output from the counter_fifo module's output port "out_readdata"?
In short, I would like to verify that the output from the counter_fifo module is same as the output from the counter module which counts upto say 100 (because counter_fifo is a combination of counter and FIFO modules. And counter module is supposed to feed data to the FIFO and have to get out put though the FIFO output).
What are the modifications I have to do in ../Counter_FIFO/counter_fifo/sim/testbench counter_fifo_tb.v or some other files to get the similar counter output through the counter_fifo module? or this something out of scope of the simulation?
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