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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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How to simulate a design created in Platform Designer System

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design that is created using Platform Designer System. I would like to elaborate a bit: my counter.v module is co...
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,

    The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.

    Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.

    Thanks,

    Best Regards,

    Sheng

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you for your reply.

Yes, I have used the VHDL simulation file same as the synthesis file (counter.v) while developing the custom IP.

I assume you were asking about the _hw.tcI file (related to the custom component)? . Also, I can see a msim_setup.tcl file in Project Folder/Qsys_system_name/sim/mentor (Assuming it contains setup script for the simulation for the entire design?). I am attaching the _hw.tcl file with this message.

I am attaching a compressed version (.zip) of my Project Folder. The counter.v is my verilog code for counter component and is used to make the custom IP counter_module.

1) Is it mandatory to have a user-defined Top-level HDL file of the design in the Project Folder (something like .v file created by Terasic System Builder tool, in the Project Folder of DE5a-NET-DDR4 example designs)? . I am bit confused as this project compiled without a user defined top-level module. But I thought that setting counter_fifo.qsys file as top-level entity worked as it includes the /Counter_FIFO/counter_fifo/synth/counter_fifo.sv (Please refer attached image Capture.PNG) . The files included in my Quartus project is screenshotted and attached as Capture.PNG

2) May I know the .sv file in Project Folder/Qsys_system_name/synth will have the similar role of PLL_RAM.v in the example design you sent me https://www.intel.com/content/www/us/en/docs/programmable/683305/19-4/simulation-quick-start.html here.

3) Since my Project Folder/Qsys_system_name/sim/ folder contains only one .sv file, I assume my Project Folder/Qsys_system_name/sim/mentor/msim_setup.tcl file should include this file only, right? or am I still missing something? (I mean just this line, vlog -vlog01compat -work work C:/Users/abc/Desktop/Counter_FIFO/counter_fifo/sim/counter_fifo.sv)

4) Then I assume I need a testbench file similar to that in the example sent by you, to simulate my coustom IP + IP design?

It would be great if you could point the "user design files and testbench files" needed to source in the msim_setup.tcl in this case. It would be helpful for me to comprehend it well.

Thank you.