Forum Discussion
Occasional ContributorHow to simulate a design created in Platform Designer System
Hi,
The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.
Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.
Thanks,
Best Regards,
Sheng
Super ContributorHi,
"Project Folder/Qsys_system_name_tb/" is for BFM which is the ip in platform designer under category Basic Funtions -> Simulation; Debug and Verification -> Simulation and also need further the test program to simulate.
"Project Folder/Qsys_system_name/synth" is the files for synthesis. "Project Folder/Qsys_system_name/sim" is the files for simulation. Both path folders should contain the same top-level wrapper .v files if you opted for verilog in simulation option in platform designer Generate HDL GUI. Have you do like this for custom ip https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/specify-files-for-simulation-in-the.html? Is just "Project Folder/Qsys_system_name/sim" got simulation setup script .tcl compared to "Project Folder/Qsys_system_name/synth". May be you can try with one Intel ip and see.
Thanks,
Best Regards,
Sheng
