Forum Discussion
Occasional ContributorHow to simulate a design created in Platform Designer System
Hi,
The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.
Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.
Thanks,
Best Regards,
Sheng
Occasional ContributorThank you for sending the example codes!
I still have a couple of doubts and great if you could address them.
1) May I know what "Project Folder/Qsys_system_name_tb/" used for? (which have ip and Qsys_system_name_tb in it )and created in it after generate test bench in platform designer. Also does the "Project Folder/Qsys_system_name/synth" file contains design files? Sorry I have a hard time to understand it.
2) From your last message-- "The design files mean the .v files in the Project Folder/Qsys_system_name/sim folder." .v file, you meant system verilog, right? (I could locate an .sv file in that folder even if I opted for verilog in simulation option inplatform designer Generate HDL GUI)
3) And I assume "Project Folder/Qsys_system_name/sim" contains the .v or .sv files created by Quartus Prime Pro and is optimized for the simulation?
4) I also have a basic question too, I know when we use the system builder tool is used to get a design and a toplevel .v is created. But when we use the Platform Designer system to design a system, is there tool that automatically generate a top-level module? or we have to manually create a top-level .v file and instantiate the .v file created in "Project Folder/Qsys_system_name/synth" during "Generate HDL" process in the Platform Designer?
