Forum Discussion
Occasional ContributorHow to simulate a design created in Platform Designer System
Hi,
The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.
Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.
Thanks,
Best Regards,
Sheng
Super ContributorHi,
Since your design only involved IP. In platform designer Generate HDL GUI, if you have enable the Create simulation model under Simulation section, there should be Project Folder/Qsys_system_name/sim folder generated.
The design files mean the .v files in the Project Folder/Qsys_system_name/sim folder. And source the simulation setup script (msim_setup.tcl) in the Project Folder/Qsys_system_name/sim/mentor folder. Yup, "except IP design" in above quote means .ip files.
Yup, user have to write testbench additionally. Check this link https://www.intel.com/content/www/us/en/docs/programmable/683305/19-4/simulation-quick-start.html for example design download.
Check this also https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/specify-files-for-simulation-in-the.html
To support Platform Designer system generation for your custom component, you must specify VHDL or Verilog simulation files. In most cases, these files are the same as the synthesis files. To use your synthesis files as your simulation files, click Copy From Synthesis Files.
Thanks,
Best Regards,
Sheng
