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Altera_Forum's avatar
Altera_Forum
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12 years ago

How to share one PLL and DLL by two DDR3 interfaces

Hi Folks, I have a Cyclone V GX FPGA Development Board. There are six DDR3 components on the board, three are on the bottom side of 5CGXFC7D6F31C7NES and the others are on the right side. Now I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

First, I have to admit that I haven't been checking your QAR out. I just wanted to check if you have tried to assign the clock signal to a global net rather than a dual-regional one. Maybe you have selected to use an interface on the bottom left together with an interface on the top right?

Regards

J