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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

how to set timing constraints for source synchronous inputs

based on AN433 page 43~44.

Question 1:

We define both virtual clock and input clock here.

I think input clock is enough for timing constraint.

Why need both?

Question 2:

We define both input clock and generated clock after pll.

Then we which one should be used for define set_input_delay for data_in?

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  • XQSHEN's avatar
    XQSHEN
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    One more question for AN433 page46.

    what's the unit interval here?

  • Farabi_Altera's avatar
    Farabi_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Thanks Strell for sharing your knowledge. Intel support community appreciated your help.


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    regards,

    Farabi