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Altera_Forum's avatar
Altera_Forum
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9 years ago

How to set automatic values in *.tcl files (automatic maxChannel in my case)

I would like to reuse a custom component with an adjustable channel width parameter (added to the Qsys IP catalog).

The problem when using it is that the associated *.tcl file has a static value for maxChannel and keeps throwing errors: 

...
set_interface_property snk maxChannel 65535
....

Whats the simple way to have my *.tcl maxChannel be adjusted by the parameter within my HDL file? Or will I have to build a separate component each time I have a different channel width?

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I figured it out...unless there is a better way...

    I used the Altera IP tcl for the Single Clock FIFO (SC FIFO) located at [install dir]/altera/16.0/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl.

    I added the code, to include the adding of new parameters, and the elaborate{} function. This also required that I roll up the following interfaces into the elaborate{} function. It seems to work. However, because I modified the tcl file, I can no longer edit the component in Qsys; I must maintain it manually with the tcl script, which is a shame. At any rate, all errors disappear and the maxChannel and empty interface ports and parameters are set automatically according to my specified channel width.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Simpler solution: when you create a custom component using the Qsys Component Editor, on the Parameters tab, set the parameter to Editable. You can also set the default value for the parameter or just use the default value from the HDL code. This way you don't have to edit the _hw.tcl file (unless you need more advanced parameter value checking).

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    sstrell,

    Wow, that seems much simpler. However, maxChannels is not a parameter from the HDL; it's more for Qsys during Avalon-ST interface generation. In Component Editor, when I add & analyze my Verilog code, then go to the parameter tab, only the parameters from the Verilog file are shown. There's no way to add or configure maxChannels...
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Oh, I thought you were talking about your own parameter called maxChannels. Yes, you would need an elaboration callback in the hw.tcl file, like this for example:

    set_module_property ELABORATION_CALLBACK my_elaboration_callback

    proc my_elaboration_callback {} {

    if { [ get_parameter_value ENABLE_STREAM_OUTPUT ] == "false" } {

    set_port_property aso_data TERMINATION true

    set_port_property aso_valid TERMINATION true

    set_port_property aso_ready TERMINATION true

    set_port_property aso_ready TERMINATION_VALUE 0

    }

    }
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I see. And in that case, I'm assuming the module would then become uneditable with Qsys component editor? (which kinda makes sense because it would no longer follow the template for the way it works in an automated fashion).

    At least tcl scripting doesn't seem too difficult...
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Yes, once you edit the hw.tcl file, you can't go back to using the Component Editor because it will overwrite your manual edits.