Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI figured it out...unless there is a better way...
I used the Altera IP tcl for the Single Clock FIFO (SC FIFO) located at [install dir]/altera/16.0/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl. I added the code, to include the adding of new parameters, and the elaborate{} function. This also required that I roll up the following interfaces into the elaborate{} function. It seems to work. However, because I modified the tcl file, I can no longer edit the component in Qsys; I must maintain it manually with the tcl script, which is a shame. At any rate, all errors disappear and the maxChannel and empty interface ports and parameters are set automatically according to my specified channel width.