Forum Discussion
Altera_Forum
Honored Contributor
9 years agosstrell,
Wow, that seems much simpler. However, maxChannels is not a parameter from the HDL; it's more for Qsys during Avalon-ST interface generation. In Component Editor, when I add & analyze my Verilog code, then go to the parameter tab, only the parameters from the Verilog file are shown. There's no way to add or configure maxChannels...