Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

How to set analog delay MaxPlusII

Hi, I need to set a delay following a rising_edge of a sig_a. In order to do that, I have utilized the: c<=sig_a; x <= c after# nS; -- where I can select the# through a data on the bus. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I am simulating the above code, but compiler is warning for:

--- Quote Start ---

Warning: Design contains 4 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "sig_go"

Warning (15610): No output dependent on input pin "sel[0]"

Warning (15610): No output dependent on input pin "sel[1]"

Warning (15610): No output dependent on input pin "sel[2]"

Warning: No paths found for timing analysis

--- Quote End ---

Analyzing it with Modelsim-altera... no changes on output while changing sig_go.

Pls, could you help?

Thanks