How to set analog delay MaxPlusII

Thanks for ur reply,

I tried that statment yesterday while reading the manual, but simulator is not showing any delay.

I believe is due to the standard simulator I am utilizing, and I think I should utilize the post fitting one (verilog?). If so I need to ur help in picking and setting that because from the manual I am still not able to make it working (error with "executable" file not found???, this simulator is not so intuitive...).

CPLD I am utilizing is a EPM7128-10 and f=100Mhz.

code I wrote is below... but it doesn't show any "pulse", could you help?:

library ieee;
use ieee.std_logic_1164.all;
entity analog_delay is
port(
	sig_go: in std_logic;
	sel: in std_logic_vector(2 downto 0);
	z: out std_logic
);
end analog_delay;
architecture delay_ns of analog_delay is
	signal a,b,c,d,e,f,g,y: std_logic;
	attribute syn_keep: boolean;
	attribute syn_keep of a,b,c,d,e,f,g: signal is true;
begin
	sel_delay: process (sig_go,sel,a,b,c,d,e,f,g,y)
	begin
		-- delay input signal
		a <= not(not(not( not sig_go)));
		b <= not (not a);
		c <= not (not b);
		d <= not (not c);
		e <= not (not d);
		f <= not (not e);
		g <= not (not f);	
		-- mux select delay_ns
		case sel is
			when "000" => y <= sig_go;
			when "001" => y <= a;
			when "010" => y <= b;
			when "011" => y <= c;
			when "100" => y <= d;
			when "101" => y <= e;
			when "110" => y <= f;
			when "111" => y <= g;
		end case;
		
		-- results: pulse
		z <= sig_go and (not y);
	
	end process sel_delay;
end delay_ns;

Thanks a lot for ur help and contribution in making it working...