How to set analog delay MaxPlusII

I mentioned the basic method in my previous post, it' by synthesis attributes.

The syntax is documented in the Quartus manual, it's basicly like below

signal my_wire: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of my_wire: signal is true;

You can expect to need about 4 or 5 logic cells per 1 ns delay with Cyclone III FPGA, the MAX II value should be similar. For a compact coding, you can apply the synthesis attribute to a std_logic_vector rather than individuals signals.