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Altera_Forum's avatar
Altera_Forum
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17 years ago

How to set analog delay MaxPlusII

Hi, I need to set a delay following a rising_edge of a sig_a. In order to do that, I have utilized the: c<=sig_a; x <= c after# nS; -- where I can select the# through a data on the bus. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the reply.

I tried with Quartus web edition, but I have the same result...

VHDL compiler recognize the "after" keyword, but I see want gnerate any delay, my question is why it is anable that?

Anyway, is there a way to insert a "chain" of buffer in order to obtain a delay by 1nS? I don't need to be precise, I mean +/- 1nS is OK too.

I wrote below code, but simulator doesn't show any "pulse" (should I change the quartus default one?)

a <= sig_in;

b <= not (not a);

c <= b;

d <= not (not c);

x <= b and not d;

Thanks for your help.