How to set analog delay MaxPlusII

The VHDL analog delay statements are usable for simulation only. I think, this simple fact is mentioned in any serious VHDL textbook. The reason is simple as well: Programmable logic has no suitable hardware to generate delays. The usual way is to generate them synchronously between clock edges.

Generating short and adjustable delays in FPGA or CPLD isn't that easy. A CPLD has no PLL to multiply the input clock to e. g. 500 MHz that allows 1 or 2 ns delay steps like a FPGA does.

I understand from your post, that you also tried to use logic cell delay lines. If I remember right, MaxPlus II does not generally remove redundant logic cells in synthesis. Quartus in contrast does, but you have synthesis atributes to define precisely which logic cells should be kept in synthesis. I'm not sure about MaxPlus II support of synthesis attributes, thus I suggest to use Quartus, if you find no means to define delay lines in MaxPlus II.

You should be aware, that you are leaving the straight way of synchronous logic synthesis with the delay chain approach. You should know, what you re doing and probably have to ignore some compiler warnings.