How to save wire or register in schematic design

Hi,

Is there any ways to save a wire and register without optimizing & sythesizing away some internal signals after compiling the design? My project is designed via schematic (.bdf) instead of writting in HDL codes.

I know in verilog:

To save a wire:

wire my_wire /* synthesis keep = 1 */;

To save reg:

reg my_reg /* synthesis syn_preserve = 1 */;

How to keep the wire/register in schematic design so that we can see these signals in Quartus II timing simulation?

Thanks for anyone quick response........