Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

How to reduce Interconnect Delay?!

Hi,

I have designed a mux in Cyclone IV-E device.

I need to meet the Pin to Pin delay constraint of 10 ns.

Tools used are Quartus II 14.0 and Timequest.

I am geting data path with delay of 13.309ns...IC delay of this path is found to be ~7.5ns:(:confused:

Part of report is added below.

Slack

From Node

To Node

Launch Clock

Latch Clock

Relationship

Clock Skew

Data Delay

-3.309

unc_jtag_tdi

tdi_unc2

n/a

n/a

10

0

13.309

Is it possible to reduce this delay?

The logic implemented is a combo mux!

I have even tried a direct pin to pin mapping wihout any logic...and data delay is 7.496 for that(IC Delay is 3.640ns)!!

Thanks,

Neeraj G N

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Why do launch and latch clocks say n/a?

    Can you post code and relevant SDC?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Hi sstrell,

    Thanks for your time.

    Launch and latch clock is not present because its an input to output data path.

    code is added below, all signals are I/O s.

    always @(jtag_mux_sel or unc_jtag_tdi or unc_jtag_trst_l or unc_jtag_tms or unc_jtag_tck or tdo_unc0 or tdo_unc1 or tdo_unc2 or tdo_unc3)

    begin

    case(jtag_mux_sel)

    2'b00:begin

    unc_jtag_tdo = tdo_unc0;

    tdi_unc0 = unc_jtag_tdi;

    trst_l_unc0 = unc_jtag_trst_l;

    tms_unc0 = unc_jtag_tms;

    tck_unc0 = unc_jtag_tck;

    tdi_unc1 = 1'b0;

    trst_l_unc1 = 1'b0;

    tms_unc1 = 1'b0;

    tck_unc1 = 1'b0;

    tdi_unc2 = 1'b0;

    trst_l_unc2 = 1'b0;

    tms_unc2 = 1'b0;

    tck_unc2 = 1'b0;

    tdi_unc3 = 1'b0;

    trst_l_unc3 = 1'b0;

    tms_unc3 = 1'b0;

    tck_unc3 = 1'b0;

    end

    2'b01:begin

    tdi_unc0 = 1'b0;

    trst_l_unc0 = 1'b0;

    tms_unc0 = 1'b0;

    tck_unc0 = 1'b0;

    unc_jtag_tdo = tdo_unc1;

    tdi_unc1 = unc_jtag_tdi;

    trst_l_unc1 = unc_jtag_trst_l;

    tms_unc1 = unc_jtag_tms;

    tck_unc1 = unc_jtag_tck;

    tdi_unc2 = 1'b0;

    trst_l_unc2 = 1'b0;

    tms_unc2 = 1'b0;

    tck_unc2 = 1'b0;

    tdi_unc3 = 1'b0;

    trst_l_unc3 = 1'b0;

    tms_unc3 = 1'b0;

    tck_unc3 = 1'b0;

    end

    2'b10:begin

    tdi_unc0 = 1'b0;

    trst_l_unc0 = 1'b0;

    tms_unc0 = 1'b0;

    tck_unc0 = 1'b0;

    tdi_unc1 = 1'b0;

    trst_l_unc1 = 1'b0;

    tms_unc1 = 1'b0;

    tck_unc1 = 1'b0;

    unc_jtag_tdo = tdo_unc2;

    tdi_unc2 = unc_jtag_tdi;

    trst_l_unc2 = unc_jtag_trst_l;

    tms_unc2 = unc_jtag_tms;

    tck_unc2 = unc_jtag_tck;

    tdi_unc3 = 1'b0;

    trst_l_unc3 = 1'b0;

    tms_unc3 = 1'b0;

    tck_unc3 = 1'b0;

    end

    2'b11:begin

    tdi_unc0 = 1'b0;

    trst_l_unc0 = 1'b0;

    tms_unc0 = 1'b0;

    tck_unc0 = 1'b0;

    tdi_unc1 = 1'b0;

    trst_l_unc1 = 1'b0;

    tms_unc1 = 1'b0;

    tck_unc1 = 1'b0;

    tdi_unc2 = 1'b0;

    trst_l_unc2 = 1'b0;

    tms_unc2 = 1'b0;

    tck_unc2 = 1'b0;

    unc_jtag_tdo = tdo_unc3;

    tdi_unc3 = unc_jtag_tdi;

    trst_l_unc3 = unc_jtag_trst_l;

    tms_unc3 = unc_jtag_tms;

    tck_unc3 = unc_jtag_tck;

    end

    default:begin

    unc_jtag_tdo = tdo_unc0;

    tdi_unc0 = unc_jtag_tdi;

    trst_l_unc0 = unc_jtag_trst_l;

    tms_unc0 = unc_jtag_tms;

    tck_unc0 = unc_jtag_tck;

    tdi_unc1 = 1'b0;

    trst_l_unc1 = 1'b0;

    tms_unc1 = 1'b0;

    tck_unc1 = 1'b0;

    tdi_unc2 = 1'b0;

    trst_l_unc2 = 1'b0;

    tms_unc2 = 1'b0;

    tck_unc2 = 1'b0;

    tdi_unc3 = 1'b0;

    trst_l_unc3 = 1'b0;

    tms_unc3 = 1'b0;

    tck_unc3 = 1'b0;

    end

    endcase

    end

    # ###SDC is added below####

    set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc0}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc1}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc3}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc0}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc1}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc2}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc3}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc0}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc1}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc2}] 10.000

    set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc3}] 10.000

    set_max_delay -from [get_ports {tdo_unc0}] -to [get_ports {unc_jtag_tdo}] 10.000

    set_max_delay -from [get_ports {tdo_unc1}] -to [get_ports {unc_jtag_tdo}] 10.000

    set_max_delay -from [get_ports {tdo_unc2}] -to [get_ports {unc_jtag_tdo}] 10.000

    set_max_delay -from [get_ports {tdo_unc3}] -to [get_ports {unc_jtag_tdo}] 10.000

    set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc0}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc1}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc3}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc0}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc1}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc2}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc3}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc0}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc1}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc2}] 5.000

    set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc3}] 5.000

    set_min_delay -from [get_ports {tdo_unc0}] -to [get_ports {unc_jtag_tdo}] 5.000

    set_min_delay -from [get_ports {tdo_unc1}] -to [get_ports {unc_jtag_tdo}] 5.000

    set_min_delay -from [get_ports {tdo_unc2}] -to [get_ports {unc_jtag_tdo}] 5.000

    set_min_delay -from [get_ports {tdo_unc3}] -to [get_ports {unc_jtag_tdo}] 5.000

    Thanks,

    Neeraj
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    I'm pretty sure you'd need to constrain the two pins to a virtual clock, otherwise I don't think Quartus is actually going to treat that as a timed path.