Altera_ForumHonored Contributor7 years agoHow to reduce Interconnect Delay?! Hi, I have designed a mux in Cyclone IV-E device. I need to meet the Pin to Pin delay constraint of 10 ns. Tools used are Quartus II 14.0 and Timequest. I am geting data path with delay o...Show More
Altera_ForumHonored Contributor7 years agoWhy do launch and latch clocks say n/a? Can you post code and relevant SDC?
Recent DiscussionsHelp with BTS and .sof example files for Agilex 7 AGM039EAQuartus Prime Pro 25.1 fatal error during fitter: Windows "Efficiency mode" requiredQuartus Pro simulation libraries for Riviera ProRoHS declaration of 10M50DDF256C8GRequest for COO info