How to reduce Interconnect Delay?!

Hi sstrell,

Thanks for your time.

Launch and latch clock is not present because its an input to output data path.

code is added below, all signals are I/O s.

always @(jtag_mux_sel or unc_jtag_tdi or unc_jtag_trst_l or unc_jtag_tms or unc_jtag_tck or tdo_unc0 or tdo_unc1 or tdo_unc2 or tdo_unc3)

begin

case(jtag_mux_sel)

2'b00:begin

unc_jtag_tdo = tdo_unc0;

tdi_unc0 = unc_jtag_tdi;

trst_l_unc0 = unc_jtag_trst_l;

tms_unc0 = unc_jtag_tms;

tck_unc0 = unc_jtag_tck;

tdi_unc1 = 1'b0;

trst_l_unc1 = 1'b0;

tms_unc1 = 1'b0;

tck_unc1 = 1'b0;

tdi_unc2 = 1'b0;

trst_l_unc2 = 1'b0;

tms_unc2 = 1'b0;

tck_unc2 = 1'b0;

tdi_unc3 = 1'b0;

trst_l_unc3 = 1'b0;

tms_unc3 = 1'b0;

tck_unc3 = 1'b0;

end

2'b01:begin

tdi_unc0 = 1'b0;

trst_l_unc0 = 1'b0;

tms_unc0 = 1'b0;

tck_unc0 = 1'b0;

unc_jtag_tdo = tdo_unc1;

tdi_unc1 = unc_jtag_tdi;

trst_l_unc1 = unc_jtag_trst_l;

tms_unc1 = unc_jtag_tms;

tck_unc1 = unc_jtag_tck;

tdi_unc2 = 1'b0;

trst_l_unc2 = 1'b0;

tms_unc2 = 1'b0;

tck_unc2 = 1'b0;

tdi_unc3 = 1'b0;

trst_l_unc3 = 1'b0;

tms_unc3 = 1'b0;

tck_unc3 = 1'b0;

end

2'b10:begin

tdi_unc0 = 1'b0;

trst_l_unc0 = 1'b0;

tms_unc0 = 1'b0;

tck_unc0 = 1'b0;

tdi_unc1 = 1'b0;

trst_l_unc1 = 1'b0;

tms_unc1 = 1'b0;

tck_unc1 = 1'b0;

unc_jtag_tdo = tdo_unc2;

tdi_unc2 = unc_jtag_tdi;

trst_l_unc2 = unc_jtag_trst_l;

tms_unc2 = unc_jtag_tms;

tck_unc2 = unc_jtag_tck;

tdi_unc3 = 1'b0;

trst_l_unc3 = 1'b0;

tms_unc3 = 1'b0;

tck_unc3 = 1'b0;

end

2'b11:begin

tdi_unc0 = 1'b0;

trst_l_unc0 = 1'b0;

tms_unc0 = 1'b0;

tck_unc0 = 1'b0;

tdi_unc1 = 1'b0;

trst_l_unc1 = 1'b0;

tms_unc1 = 1'b0;

tck_unc1 = 1'b0;

tdi_unc2 = 1'b0;

trst_l_unc2 = 1'b0;

tms_unc2 = 1'b0;

tck_unc2 = 1'b0;

unc_jtag_tdo = tdo_unc3;

tdi_unc3 = unc_jtag_tdi;

trst_l_unc3 = unc_jtag_trst_l;

tms_unc3 = unc_jtag_tms;

tck_unc3 = unc_jtag_tck;

end

default:begin

unc_jtag_tdo = tdo_unc0;

tdi_unc0 = unc_jtag_tdi;

trst_l_unc0 = unc_jtag_trst_l;

tms_unc0 = unc_jtag_tms;

tck_unc0 = unc_jtag_tck;

tdi_unc1 = 1'b0;

trst_l_unc1 = 1'b0;

tms_unc1 = 1'b0;

tck_unc1 = 1'b0;

tdi_unc2 = 1'b0;

trst_l_unc2 = 1'b0;

tms_unc2 = 1'b0;

tck_unc2 = 1'b0;

tdi_unc3 = 1'b0;

trst_l_unc3 = 1'b0;

tms_unc3 = 1'b0;

tck_unc3 = 1'b0;

end

endcase

end

# ###SDC is added below####

set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc0}] 10.000

set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc1}] 10.000

set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 10.000

set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc3}] 10.000

set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc0}] 10.000

set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc1}] 10.000

set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc2}] 10.000

set_max_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc3}] 10.000

set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc0}] 10.000

set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc1}] 10.000

set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc2}] 10.000

set_max_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc3}] 10.000

set_max_delay -from [get_ports {tdo_unc0}] -to [get_ports {unc_jtag_tdo}] 10.000

set_max_delay -from [get_ports {tdo_unc1}] -to [get_ports {unc_jtag_tdo}] 10.000

set_max_delay -from [get_ports {tdo_unc2}] -to [get_ports {unc_jtag_tdo}] 10.000

set_max_delay -from [get_ports {tdo_unc3}] -to [get_ports {unc_jtag_tdo}] 10.000

set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc0}] 5.000

set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc1}] 5.000

set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 5.000

set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc3}] 5.000

set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc0}] 5.000

set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc1}] 5.000

set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc2}] 5.000

set_min_delay -from [get_ports {unc_jtag_tdi}] -to [get_ports {tdi_unc3}] 5.000

set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc0}] 5.000

set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc1}] 5.000

set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc2}] 5.000

set_min_delay -from [get_ports {unc_jtag_tms}] -to [get_ports {tms_unc3}] 5.000

set_min_delay -from [get_ports {tdo_unc0}] -to [get_ports {unc_jtag_tdo}] 5.000

set_min_delay -from [get_ports {tdo_unc1}] -to [get_ports {unc_jtag_tdo}] 5.000

set_min_delay -from [get_ports {tdo_unc2}] -to [get_ports {unc_jtag_tdo}] 5.000

set_min_delay -from [get_ports {tdo_unc3}] -to [get_ports {unc_jtag_tdo}] 5.000

Thanks,

Neeraj