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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to reduce HUGE clock delays (Cyclone V)

Hi all,

I am working on a design on a Cyclone V chip. It is a 5CEFA9F23C8.

I am doing some experiments with timing constraints and this is a situation I ran into.

My experiment is simple, I have a output register that toggles and it is clocked by my input clock. However, referring to the attached image:

Ignore the green positive slack. If you take a look at the highlighted part. It shows a clock delay of 5.1 ns.

The clock is 100 MHz, hence it is 10 ns, 5.1 ns delay is more than half the clock period.

I suspect this is not normal and hence am looking for help here.

My data path is (dedicated clk pin => output register => IO)

Anyone know what's the issue here? Where might the delay be coming from? And how can I reduce this delay if at all possible?

Thanks in advance!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It doesn't sound abnormal. The clock network in the FPGA introduces a delay. If this is more than you can handle, then you need to specify in the time constraints the maximum delay that you can handle. Then if Quartus can't meet your timing requirement, you'll probably need to feed your clock input into a pll, from it generate an output with a delay and adjust the delay until you get what you want.

    But are you sure you need this? Usually as long as the receiving component gets its signal before the rising edge of the clock, everything is fine.