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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to rectify modelsim error "failed to open top_core.vo"?

I was trying to simulate PCI Express reference design as per instructions given in "ip compiler for pci express" (https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0cb4qfjaaahuke...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

There are two things.

Either you are running a Gate level sim only one netlist file (.vo ) is required.

If you are running RTL functional simulation then all (.v) files are required.

So which one are you running?