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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to rectify modelsim error "failed to open top_core.vo"?

I was trying to simulate PCI Express reference design as per instructions given in "ip compiler for pci express" (https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0cb4qfjaaahukewi308hcypphahveky4khbzicio&url=https%3a%2f%2fwww.altera.com%2fliterature%2fug%2fug_pci_express.pdf&ei=tt3cvbeggmsiugs8xapqca&usg=afqjcnh70svgqfxfxgufql7dgu2ix29uxa&sig2=jt7ej5ksplgilqimjejsqq&bvm=bv.99556055,d.c2e&cad=rja) document. Reference design file I downloaded from altera website and copied in the system. When runtb.do file is runned an error message "failed to open top_core.vo" is shown in the screen.

Attaching snapshot of error message here.

https://www.alteraforum.com/forum/attachment.php?attachmentid=10968

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    Are you using Native link for simulation or standalone simulation?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    What is the difference between Native link for simulation and standalone simulation? I am using standalone Modelsim, not from Quartus link. I hope this is what you meant. If my assumption is wrong let me know.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Yes that is what I meant,

    Now looks like you are trying to run a gate level simulation..

    Can you double check if you have created the netlist successfully and the file is present at the location mentioned in .do file.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Net list is created succesfully. Even top.vo (top module) file is there in the respective location. But this .do file is looking for top_core.vo which is part the project (top_core.v file is also available in the respective location).

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    There are two things.

    Either you are running a Gate level sim only one netlist file (.vo ) is required.

    If you are running RTL functional simulation then all (.v) files are required.

    So which one are you running?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Make change in the .do file according to your requirement i-e give all of your design files as input (either Netlist files or design files)

    And then try running simulation.

    I hope this will help you.

    Cheers,

    Have a nice weekend :)
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I tried that it is working. Thank you. Hopes simulating either .v instead of .vo won't make much difference.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You have to simulate one of them at a time, since they both are simulating same module only difference is with different level of abstraction.

    simulating .v is your RTL simulation

    simulating .vo is synthesized netlist simulation

    There won't be any difference, unless you use the gate delays.

    To understand the difference you can read in detail about gate level simulation (.vo) vsfunctional simulation.