Forum Discussion
RobertLiang
Occasional Contributor
Occasional ContributorHow to realize “posedge asynchronous reset logic” in verilog?
i know high level async reset can be achieved like:
always@(posedge clk or posedge rst)
begin
if (rst==1)
but how to realize posedge async reset, which means the moment reset edge coming u...
Hi Robert,
You have to deassert the reset signal, LOW signal in your case. Otherwise, the logic cannot come out from reset state.
Thanks.
Best regards,
KhaiY
RobertLiangOccasional Contributor
Occasional Contributorthank you!
but, what i want to achieve is to posedge reset rather than high level reset.
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Robert,
You have to deassert the reset signal, LOW signal in your case. Otherwise, the logic cannot come out from reset state.
Thanks.
Best regards,
KhaiY
