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RobertLiang's avatar
RobertLiang
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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How to realize “posedge asynchronous reset logic” in verilog?

i know high level async reset can be achieved like: always@(posedge clk or posedge rst) begin if (rst==1) but how to realize posedge async reset, which means the moment reset edge coming u...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi Robert,

    You have to deassert the reset signal, LOW signal in your case. Otherwise, the logic cannot come out from reset state.

    Thanks.

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


The logic will not come out from reset state if you do not deassert the reset signal.


Thanks.

Best regards,

KhaiY


  • RobertLiang's avatar
    RobertLiang
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    thank you!

    but, what i want to achieve is to posedge reset rather than high level reset.

    • KhaiChein_Y_Intel's avatar
      KhaiChein_Y_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi Robert,

      You have to deassert the reset signal, LOW signal in your case. Otherwise, the logic cannot come out from reset state.

      Thanks.

      Best regards,

      KhaiY