Occasional ContributorHi Robert,
You have to deassert the reset signal, LOW signal in your case. Otherwise, the logic cannot come out from reset state.
Thanks.
Best regards,
KhaiY
Super ContributorIt's not clear what you're trying to achieve here. Your first example is the way to do this. rst_pre in your second example is never going to be low because you have posedge rst in your sensitivity list (rst is high) and then assigning that to rst_pre.
Perhaps you are saying that your rst signal is truly asynchronous (pushbutton not debounced?), meaning that it could be glitching and causing issues. If this is the case, you should register it, synchronizing it to a clock domain before using it in the sensitivity list here.
If you have a Signal Tap waveform that shows the issue you're talking about, you could post it.
#iwork4intel
Occasional Contributorthank you, your suggestion( which indeed help) like the waveform below. i extended 'rst_in' to clock edge to register it.
But what i want is to 'reset my logic immediately after posedge of rst_in', and do not reset when the next clock edge arrives.
if i use the logic below, the logic will be reset more than one time, if the high level rst_in last for a long time.
always @ (posedge clk or posedge rst_in ) begin if (rst_in) ...
you said the second logic i mentioned can't achieve that, but i think: the moment the posedge rst_in arrives, 'rst_pre' will not change immediately because i use '<=' rather than '='. so it will still keep the value of 0, while 'rst_in' is 1.
thank you for your help! maybe my question is weird (i just too eager to know the answer...)
