How to read data from a memory location where ADC conversion result is stored?

Hi Alex,

Thanks for your reply. I solved the problem. I was using static signals and now when i pulsed the start of packet and kept the command valid high all the time, it worked.

The following part of the code is for Pulse Width Modulation (PWM) generator.What i intended to do earlier, is to read ADC data and use it to change the duty-cycle(or ON Time) of my pulse. Since, I was not ale to read ADC data, it kept it fixed earlier. The bottom code generates a counter for PWM.

As, now I can read the ADC data, I am able to change this duty-cycle.

Also, this code is not for university tutorial. It is for the industry. I am very new to VHDL coding and using FPGAs but certainly with your help I was able to correctly configure my ADC.

Thanks again for your help!

Regards,

Misha

Code:

.....

process(shadowload,count)

begin

if (shadowload > count) then

Su <= '0' ;

Sb <= '1' after deadtime;

else

Sb <= '0';

Su <= '1' after deadtime;

end if;

end process;

What relevance does the following code have to your ADC? Perhaps none, but that means there isn't any logic left!

Code:

process(clk_clk)

begin

if(rising_edge(clk_clk)) then

if(count = PRD) then

count <= to_unsigned(1,12);

shadowload <= CMP;

else

count <= count + 1;

end if;

end if;

end process;

Code: