How to read data from a memory location where ADC conversion result is stored?

I feel there's quite a bit lacking in your code... You mention logic tap - can I assume you're trying to put this onto some hardware?

In your entity declaration - 'Su' & 'Sb', your hardware's only I/O, has nothing to do with the ADC. Is this intentional?

entity ADC_PWM is
    Port (
        clk_clk : in STD_LOGIC;
             Su : out STD_LOGIC;
             Sb : out STD_LOGIC);
end ADC_PWM;

What are you hoping the following will do? It may simulate as you'd expect but it won't synthesize to anything you can put onto hardware.

        deadtime <= 500 ns;
.....
        process(shadowload,count)
            begin
            if (shadowload > count) then
                Su <= '0' ; 
                Sb <= '1' after deadtime;
                else
                Sb <= '0';
                Su <= '1' after deadtime;
            end if;
        end process;

What relevance does the following code have to your ADC? Perhaps none, but that means there isn't any logic left!

    process(clk_clk)
    begin
        if(rising_edge(clk_clk)) then
            if(count = PRD) then
                count <= to_unsigned(1,12);
                shadowload <= CMP;
            else
                count <= count + 1;
            end if;
        end if;
    end process;

        signal ready,valid,sof,eof,empty,reset : std_logic := '0';
.....
        ADC1 : ADC port map(clk_clk,Y ,channel ,Y ,N ,ready,valid,sof,eof,empty,responsechannel, data, reset);

All those signals (ready,valid,sof etc.) are output signals from the ADC. The ADC drives these signals. You shouldn't be assigning them to '0'.

None of your output signals connect to anything, except possibly your signal tap module. Signals that don't drive anything will result in chunks of logic being removed. If the ADC output signals don't actually drive anything what's to stop Quartus getting rid of it? (Yes, possibly signal tap.)

All your ADC input signals are static. When I've previously played around with the ADC I found that didn't work - I had to control something. Looking back at my code the minimum I seemed to be able to get away with was pulsing 'command_valid', but I still had to pulse it.

Your clock frequency - see table 5-1 on page 5-2 of the ADC document. Is you clock at an appropriate frequency?

Is this a University tutorial? I feel you need a chat with your tutor...

Cheers,

Alex