How to read data from a memory location where ADC conversion result is stored?

Hi Alex,

Thanks a lot for your reply. I followed what you suggested and qsys generated following example code for me. I included this code in my VHDL file.I have attached my VHDL code (at the bottom) where i want to read the data. The code is able to compile but i am not able to read the data. I used logic tap II analyzer to confirm that i am not reading ADC data. Kindly help.

component ADC is

port (

clk_clk : in std_logic := 'X'; -- clk

modular_adc_0_command_valid : in std_logic := 'X'; -- valid

modular_adc_0_command_channel : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel

modular_adc_0_command_startofpacket : in std_logic := 'X'; -- startofpacket

modular_adc_0_command_endofpacket : in std_logic := 'X'; -- endofpacket

modular_adc_0_command_ready : out std_logic; -- ready

modular_adc_0_response_valid : out std_logic; -- valid

modular_adc_0_response_startofpacket : out std_logic; -- startofpacket

modular_adc_0_response_endofpacket : out std_logic; -- endofpacket

modular_adc_0_response_empty : out std_logic; -- empty

modular_adc_0_response_channel : out std_logic_vector(4 downto 0); -- channel

modular_adc_0_response_data : out std_logic_vector(11 downto 0); -- data

reset_reset_n : in std_logic := 'X' -- reset_n

);

VHDL Code that I made:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity ADC_PWM is

Port ( clk_clk : in STD_LOGIC;

Su : out STD_LOGIC;

Sb : out STD_LOGIC);

end ADC_PWM;

architecture Behavioral of ADC_PWM is

component ADC is

port (

clk_clk : in std_logic := 'X'; -- clk

modular_adc_0_command_valid : in std_logic := 'X'; -- valid

modular_adc_0_command_channel : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel

modular_adc_0_command_startofpacket : in std_logic := 'X'; -- startofpacket

modular_adc_0_command_endofpacket : in std_logic := 'X'; -- endofpacket

modular_adc_0_command_ready : out std_logic; -- ready

modular_adc_0_response_valid : out std_logic; -- valid

modular_adc_0_response_startofpacket : out std_logic; -- startofpacket

modular_adc_0_response_endofpacket : out std_logic; -- endofpacket

modular_adc_0_response_empty : out std_logic; -- empty

modular_adc_0_response_channel : out std_logic_vector(4 downto 0); -- channel

modular_adc_0_response_data : out std_logic_vector(11 downto 0); -- data

reset_reset_n : in std_logic := 'X' -- reset_n

);

end component ADC;

signal count,shadowload,CMP : unsigned (11 downto 0) := to_unsigned(0,12);

signal deadtime : time := 500 ns;

signal PRD : unsigned (11 downto 0) := to_unsigned(4000,12);

signal Y : std_logic := '1';

signal N : std_logic := '0';

signal channel,responsechannel : std_logic_vector(4 downto 0) :=(others => '0');

signal data : std_logic_vector(11 downto 0) :=(others => '0');

signal ready,valid,sof,eof,empty,reset : std_logic := '0';

begin

CMP <= to_unsigned(2000,12);

deadtime <= 500 ns;

ADC1 : ADC port map(clk_clk,Y ,channel ,Y ,N ,ready,valid,sof,eof,empty,responsechannel, data, reset);

process(shadowload,count)

begin

if (shadowload > count) then

Su <= '0' ;

Sb <= '1' after deadtime;

else

Sb <= '0';

Su <= '1' after deadtime;

end if;

end process;

process(clk_clk)

begin

if(rising_edge(clk_clk)) then

if(count = PRD) then

count <= to_unsigned(1,12);

--shadowload <= unsigned(data);

shadowload <= CMP;

else

count <= count + 1;

end if;

end if;

end process;

end Behavioral;