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Honored Contributor
10 years agoI assume you're not using Nios. So, in Qsys configure your ADC core for 'ADC control core only'. You may well be doing this anyway. Then make sure you've exported the 'command' and 'response' Avalon Streaming interfaces. Then, when you generate your HDL, you'll end up with a set of command & response signals to connect into your design.
Then refer to figure 2-6 on page 2-9 of the max 10 analog to digital converter user guide (https://www.altera.com/literature/hb/max-10/ug_m10_adc.pdf). This shows you the timing for the Avalon streaming interfaces - which you exported - that you need to connect into your logic. You'll find your samples on the 'response_data' bus, valid when 'response_valid' indicates so. Cheers, Alex