Honored ContributorHi
I am new to Altera 13.1. I have written a OR gate VHDL code and it compiled successfully. I know how to view the waveform using Modelsim Altera. What I want to know is how to provide logic states like 0 and 1 to the inputs of OR gate. I need to see the o/p of 1 input OR gate for all the 4 possible values in the wave window.
Honored ContributorYou can use push button or DIP switch as input and user LED as a output.This is the simplest way to test your OR gate design.
Honored ContributorBut zoomkrupesh, that requires hardware. The OP asked for modelsim.
Jayanth - you need to create a testbench for your OR gate. This will be written in VHDL. But you can use non-synthesisable constructs in the coding, as you will only simulate it:
signal a,b,c : std_logic;
a <= '0', '1' after 10 ns, '0' after 20 ns;
b <= '0', '1' after 20 ns;
or_inst : entity work.my_or_gate
port map (
a <= a;
b <= b;
op <= op
);
Thank you very much Tricky. I will try that and let you know the result.
Honored ContributorSorry Janyanth,
I didn't understand your question. Whatever tricky has suggested is correct. You can also use clocks as a input of the OR gate. You can use two clocks in such a manner that frequency of one clock is double then second clock. By doing this you can test all the four possibilities.
