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Altera_Forum
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12 years ago

How to provide logic inputs?

Hi I am new to Altera 13.1. I have written a OR gate VHDL code and it compiled successfully. I know how to view the waveform using Modelsim Altera. What I want to know is how to provide logic s...
Altera_Forum's avatar
Altera_Forum
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12 years ago

But zoomkrupesh, that requires hardware. The OP asked for modelsim.

Jayanth - you need to create a testbench for your OR gate. This will be written in VHDL. But you can use non-synthesisable constructs in the coding, as you will only simulate it: 


signal a,b,c : std_logic;
a <= '0', '1' after 10 ns, '0' after 20 ns;
b <= '0',                  '1' after 20 ns;
or_inst : entity work.my_or_gate
port map (
  a <= a;
  b <= b;
  
  op <= op
);