Honored Contributor
Honored ContributorA couple of service requests to Altera revealed that the Max V component (U19) responsible for controlling FPGA configuration comes with a factory load that does not behave correctly when MSEL is set to one of the active serial configuration schemes. The Cyclone V SoC Development Board Reference Manual contains the following paragraph:
"By default, this board has a FPP configuration scheme setting. The MAX_AS_CONF pin needs to be driven from the MAX V to enable the bus switch (U13) to isolate the EPCQ flash (U20) from the configuration bus. This happens when MSEL is 10010 or 10011." According to this paragraph, the MAX V (U19) should assert the MAX_AS_CONF pin when MSEL is 10010 or 10011. Both of these MSEL settings are active serial configuration schemes. Active serial is the configuration scheme used to configure the FPGA from the EPCQ256 device, which is the device I have been trying to program with a JIC file. The problem is the factory load for U19 does not behave as indicated in this paragraph from the reference manual. Altera did provide me with a programming file (.pof) for a newer version of the Max V design that does behave correctly. This required me to use the quartus programmer to reprogram U19. After reprogramming U19, I was able to program the EPCQ256 device using a JIC file and the quartus programmer. After the EPCQ256 device was programmed, the FPGA was able to configure itself from the EPCQ256 device. As a side note, I was also able to use the sof2flash, nios2-configure-sof, and nios2-flash-programmer commands from a Nios-II command shell to program the EPCQ256 as well. This does require an FPGA sof programming file with a nios2 processor. So Peli, it turned out to be a hardware problem as you predicted. Maybe what I've learned will help someone else?
