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MGrab6
New Contributor
New ContributorHow to prevent the synthesizer from optimizing signals away? Fanout?
Using: 5M570 Max V CLPD speed grade 5. CLK_IN is and in port div_clk(3 downto 0) is a signal I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescale...
KennyT_altera
Super Contributor
Super ContributorFirstly, you need to check what are the source of your RTL? Is your source is verilog, VHDL, AHDL or schematics?
