Forum Discussion
MGrab6
New Contributor
New ContributorHow to prevent the synthesizer from optimizing signals away? Fanout?
Using: 5M570 Max V CLPD speed grade 5. CLK_IN is and in port div_clk(3 downto 0) is a signal I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescale...
KennyT_altera
Super Contributor
Super ContributorYou can archive the project to *.qar by project -> archive project.
Looking into the report files, I cannot see high fan out on the node.
What I suggest is do it on the RTL itself. You can control how much fan out you want to a particular module. This way, you can use different pll if needed for fan out issue.
MGrab6New Contributor
New ContributorIs there documentation on how to directly edit the RTL in Quartus II? I can get to the RTL viewer but can't make modificatoins there.
