Forum Discussion
MGrab6
New Contributor
New ContributorHow to prevent the synthesizer from optimizing signals away? Fanout?
Using: 5M570 Max V CLPD speed grade 5. CLK_IN is and in port div_clk(3 downto 0) is a signal I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescale...
KennyT_altera
Super Contributor
Super ContributorYou can archive the project to *.qar by project -> archive project.
Looking into the report files, I cannot see high fan out on the node.
What I suggest is do it on the RTL itself. You can control how much fan out you want to a particular module. This way, you can use different pll if needed for fan out issue.
MGrab6New Contributor
New ContributorI did not think the MAX V had a PLL?
I haven't played with the RTL view much. Although it seems far more intuitive. I take it the 12{1} means 12 of div_counter[1] into that logic block?
Mark
