Forum Discussion

MGrab6's avatar
MGrab6
Icon for New Contributor rankNew Contributor
6 years ago

How to prevent the synthesizer from optimizing signals away? Fanout?

Using: 5M570 Max V CLPD speed grade 5. CLK_IN is and in port div_clk(3 downto 0) is a signal I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescale...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

can you attached your design.qar to have a look? Basically, high fan out should not be a issue as you are using global routing. But, it might pull your whole circuit into one side if your frequencies requirement are high.

We need to look into the timing analyzer in order to further analyze the root cause.