How to preserve nets during quartus analysis/synthesis

I've seen SW pricing in the on-line store... http://www.altera.com/buy/software/buy-software.html

But remember there is web edition too, which is free but restricted: http://www.altera.com/literature/po/ss_quartussevswe.pdf

Thanks for the help.

As far as versions of Quartus is concerned, I work for a large bureaucratic company- I put in a request for an upgrade to a newer version of Quartus II back in November- the approval had to go thru five levels of approval, meanwhile, I'm stuck with this old version.

-Gary

P.S., How much does a Quartus license cost anyway?

Note that adding "keep" may add one logic cell delay in your timing path (probably not a problem, but something to keep in mind if it is a timing-critical path).

The nodes are "synthesized away" because synthesis has to translate the logic in your code to implement the function in the device logic cells - look up tables etc. The specific nodes in your code may not exist as separate nodes in the final implementation, unless you force that with the keep option. As you noted, probing the register that drives the signal can be the easiest way to find the right node without forcing logic to be preserved separately.

For other HDL syntax, check out the handbook chapter that talks about these attributes:

quartus ii integrated synthesis (http://www.altera.com/literature/hb/qts/qts_qii51008.pdf), starting around page 44. The syntax is also in QII Help, now that you know what you're looking for.

Also, I have to ask... If you are new to Quartus II, why are you starting with 5.1? That's about 4 years old... I would recommend using the latest 9.0 version to get the latest devices, enhancements, etc. There's a free web edition on the web site that you can use for smaller devices to get started...

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Hi,

I new to using Quartus- I'm using v 5.1. After doing analysis/synthesis, while setting up Quartus simulation, I notice that the user-entered node names appear to be synthesized away. In other words, to display the sim results of a node, I must choose the origin of that node. If I choose an unregistered node as a destination, it disappears from the simulation waveform window.

Any suggestions would be appreciated,

Gary

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Hi Gary,

you can use one of three synthesis attribute in order to preserve node:

in verilog:

to save a wire:

wire net1 /* synthesis keep */ ;

to save reg:

reg reg1 /* synthesis preserve */;

if the register has no fanout you have to use

reg reg1 /synthesis noprune */;

Kind regards

GPK