How to preserve nets during quartus analysis/synthesis

Note that adding "keep" may add one logic cell delay in your timing path (probably not a problem, but something to keep in mind if it is a timing-critical path).

The nodes are "synthesized away" because synthesis has to translate the logic in your code to implement the function in the device logic cells - look up tables etc. The specific nodes in your code may not exist as separate nodes in the final implementation, unless you force that with the keep option. As you noted, probing the register that drives the signal can be the easiest way to find the right node without forcing logic to be preserved separately.

For other HDL syntax, check out the handbook chapter that talks about these attributes:

quartus ii integrated synthesis (http://www.altera.com/literature/hb/qts/qts_qii51008.pdf), starting around page 44. The syntax is also in QII Help, now that you know what you're looking for.

Also, I have to ask... If you are new to Quartus II, why are you starting with 5.1? That's about 4 years old... I would recommend using the latest 9.0 version to get the latest devices, enhancements, etc. There's a free web edition on the web site that you can use for smaller devices to get started...