Honored ContributorHi,
I want to multiply the 50 kHz clock signal frequency by 2048 in order to obtain about 100MHz frequency. However, the plls of Cyclone II board are supplying at least 300MHz frequency. How can I do this multiplication by using these plls? Thank you.
Honored Contributorthe CII PLLs have a minimum input frequency of 10 MHz.
see page 66: http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdfHonored ContributorThank you thepancake (http://www.alteraforum.com/forum/member.php?u=7632), you are right. However, I can not still use this pll to multiply the frequency of my 50 kHz signal.
Is there a way to multiply it?Honored ContributorIt depends on the specification of the intended multiplied clock. Possibly a digital PLL design can be a solution. Otherwise, you have to use an external analog PLL hardware (at least phase detector and VCO).
Honored Contributoreven a digital PLL will require a high(er) speed clock, right? seems like it would make the original problem redundant.
Honored ContributorIs this an existing board or are you still designing. Your best bet is to use an external clock generator that you can "genlock" to your 50kHz clock. The external clock can either be a VCO or a digitally synthesized clock (AD9954 as an example). The important thing is you have to be able to control the frequency of it.
Then you have to write a phase detector and control the external clock to keep it locked to your 50kHz clock. How closely your generated clock tracks the 50kHz clock in phase and frequency will depend on the bandwidth of your loop filter. If you use a digital synthesis clock, I recommend using a PID controller. I don't know that you can get to a high enough frequency inside a Cyclone II to allow you to do a digital PLL. Depends on your design requirements I suppose. JakeHonored ContributorI am trying to decide which way I should follow. If I can use the plls that exist on the fpga board, I'll use them. But if I can't do this, I will design another board. I'm not familiar with PID controllers and loop filters so it seems very difficult to construct a digital pll.
Honored ContributorThe digital PLL is a different approach than the VCO. Can I ask where this 50kHz clock is coming from?
JakeHonored Contributor
