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Altera_Forum
Honored Contributor
Honored ContributorHow to manually place PLL
I've been looking through the forums and have only found one post about this. It didn't help me because I got an error when trying to follow it. My issue is that I have to modules each having their...
Altera_ForumHonored Contributor
Honored ContributorOk so I figured out why Quartus couldn't find my PLL's. I had to add a |pll1 when I used the assignment editor to select the path to each PLL. So my paths are as follows for an example:
I2CMasterController:i2c_tx_master_0|I2C_TX_Master_PLL:I2C_TX_Master_PLL_inst|altpll:altpll_component|I2C_TX_Master_PLL_altpll:auto_generated|pll1 I2C_Controller:sm5882_0|SampleClkPll:SampleClkPLL_inst|altpll:altpll_component|SampleClkPll_altpll:auto_generated|pll1 I have run into another problem after this though. Now, Quartus says the location assignments of the PLL's are not compatible -hence the PLLs can't be merged. I'm not trying to merge them. I have two PLLs I want to be seperate. Why is Quartus trying to merge these two PLLs? I only have a single 50Mhz clock in on this development board driving the input of both PLLs...is this why Quartus is trying to merge them? It seems unreasonable that you would have to have two different input clocks to achieve two seperate PLLs. Attached is my message log from the message window. The exact warnings above are in there but in full text.
