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Altera_Forum's avatar
Altera_Forum
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17 years ago

How to make the output of PLLs in differrent FPGA devices synchronous with each oth

PLLs in differrent devices have the same settings and the same clock source(as attached plot). I need the PLL output of clk1 and clk2 to be synchronous with each other. How to do it? Could you help ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi,

Fore me it seems like

Try to connect the PLLs with a dedicated line (see the board layout manual)

for Ex: CoreClk (10MHz) : in std_logic;

oClk <= CoreClk;

Take an extra port oClk : out std_logic; (in Device 1)

and iClk : in std_logic ; (in Device 2)

and also try to adjust the different phases which can be statistically set in MegaCore Wizard.