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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to make bidirectional bus in SystemVerilog

I have a bidirectional 8 bit bus for communicating between my CPLD and my main CPU. At the top level module I declared this like this (left out details of other IO stuff):

module top ( inout [7:0] gpbus, input bit rd, input bit wr );

When I drive the gpbus from my test bench it works fine. When I set the gpbus to 8'bZ it does tri-state it. However, when I drive it from inside my module nothing changes at the test bench. It stays tri-stated.

How do I correctly create and connect such a bus and simulate it? I've tried using the alias statement but no matter what I do that creates an error "near text 'alias' expecting endmodule".

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Most likely a connection error, but you did not show enough code that might give a hint at what is wrong. How are you driving the bus in your testbench and CPLD? You need to be using a continuous assignment in both places. Either

    assign gpbus = wr ? data : 8'z;

    or

    assign gpbus = data;

    And you procedurally assign data to 8'bz when that side is not driving.