Forum Discussion
Occasional ContributorHow to make a custom IP (that integrated with an example design) to create testbench in Arria 10
No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.
Occasional ContributorThank you very much for helping me. Now I could get rid of the error by adding the simulation files on the Files tab of the Component Editor (I added as a synthesis file).
As I am comparatively new to Quartus Prime, I would like to know how to simulate my design, once test-bench of a design is created using Platform Designer System. I would like to elaborate a bit: My counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and generated HDL and test benches for the design. Also I compiled the whole design in Quartus Prime Pro. May I know how I could get the simulation for the whole design? (I have model-sim with my Quartus Prime Pro 18.1.) . I have got this doubt since I am using an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design.
