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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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How to make a custom IP (that integrated with an example design) to create testbench in Arria 10

Hi, I have a custom IP of a counter and that connected to the PCIe DMA transfer example design for the Arria 10 device(I have attached the counter code counter.v with this message). I also added ...
  • sstrell's avatar
    sstrell
    2 years ago

    No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you very much for helping me. Now I could get rid of the error by adding the simulation files on the Files tab of the Component Editor (I added as a synthesis file).

As I am comparatively new to Quartus Prime, I would like to know how to simulate my design, once test-bench of a design is created using Platform Designer System. I would like to elaborate a bit: My counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and generated HDL and test benches for the design. Also I compiled the whole design in Quartus Prime Pro. May I know how I could get the simulation for the whole design? (I have model-sim with my Quartus Prime Pro 18.1.) . I have got this doubt since I am using an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design.