Forum Discussion

Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

How to make a custom IP (that integrated with an example design) to create testbench in Arria 10

Hi, I have a custom IP of a counter and that connected to the PCIe DMA transfer example design for the Arria 10 device(I have attached the counter code counter.v with this message). I also added ...
  • sstrell's avatar
    sstrell
    2 years ago

    No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you very much for the info.

    Also I would like to know is there any Quartus Prime Pro functionality to get a design file optimized for simulation (out of the synthesisable design HDL code) ?

    Also you mentioned "different design file optimized for simulation", could you give me an insight of what are those common differences in general cases- Anything coding style or something like that?

    I am bit curious that when you asked me about the component editor settings in your first message, is it about the signals and interface settings I used, or the files (synthesis file and simulation file) I used?

    Thank you very much