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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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How to make a custom IP (that integrated with an example design) to create testbench in Arria 10

Hi, I have a custom IP of a counter and that connected to the PCIe DMA transfer example design for the Arria 10 device(I have attached the counter code counter.v with this message). I also added ...
  • sstrell's avatar
    sstrell
    2 years ago

    No, the file you put in the simulation files section is the design file that should be used when the design is simulated, not a simulation testbench. This can be the same file as the synthesis file or it could be a different design file optimized for simulation.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

What are your settings in Component Editor? Perhaps you didn't add simulation files on the Files tab of the Component Editor.

Also helpful to see how your custom component is connected to the rest of the system.

  • Sijith's avatar
    Sijith
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thanks for the roping in to help me. Sorry I missed to add the simulation file while creating custom component.

    Will add and update you the result with adding them. (I am attaching my codes counter and wrote a simulation file counter_tb (I assume this is what I am suppose to do)). I have attached them as .txt files.

    As I am new to Verilog and Quartus Prime, Its highly appreciate any suggestion in the above mentioned codes that is essential for them to be compatible with the remaining part of my design in synthesis and simulation.

    As the counter code I have is for converting to custom IP and to integrate to the PCIe DMA transfer example design, do I have to have any special consideration while writing the simulation code?

    From "What are your settings in Component Editor?" your question, you meant signal and interface connection?

    Also I am attaching a block symbol of the entire design (avalon_fifo and counter_1 are the extra components I added to the PCIe DMA transfer example design), which have the counter custom IP, Avalon FIFO IP and the PCIe DMA transfer example design.

    Please let me know if you need any more information. Thank you.