New Contributorhow to interface with DAC while using ALTERA_FP_Functions, to process arithmetic operations in 32 bits single precision ?
I'm implementing a mathematical operation in Quartus using ALTERA_FP_FUNCTIONS, the input signal is coming from the ADC through low frequency generator.
To interface with the DAC TI 5672, I use IP core converter 14->32 bits float single precision, then i inverse the sign of the MSB to convert to complement two.
The question is:
As the DAC TI5672 has a limited output that cannot overpass 3.3 V, how can we fix that, to make a correspondance between the output of the IP Functions and the output range of the DAC ;
Thanks
here belw is the interface of the DAC
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
--use ieee.sTD_LOGIC_ARITH.all;
LIBRARY work;
--use work.package_adc_dac.all;
ENTITY mlp IS
port (clk: in std_logic;
-- clock_out: out std_logic;
reset: in std_logic;
enable: in std_logic;
Data_in: in std_logic_vector(13 downto 0);
Data_out: out std_logic_vector (13 downto 0)
);
end;
architecture mlp_arch of mlp is
signal count : std_logic_vector(13 downto 0);
begin
--CD: clk_divider
--port map (
--clkin => clk ,
--rst => reset ,
--clkout=> clock_out
--);
process(clk,reset)
begin
if reset='1' then
count<= (others=>'Z');
elsif rising_edge(Clk) then
if enable='1' then
count<=Data_in;
else
count<=(others=>'0');
end if;
-- if count > '1'&'1'& x"FFF" then
-- Data_out <='0'&'1'& x"FFF";
--elsif count < '0'&'0'& x"000" then
-- Data_out<='1'&'0'& x"000";
--end if;
end if;
Data_out(12 downto 0)<= count(12 downto 0);
Data_out (13) <= not count(13);
end process;
end mlp_arch;
