how to instantiate the Altera v17.0 pll in the verilog file.can i get the instantiation code.

Hi,

Correct, Please check the 'Generate' Menu of Platform Designer-> 'Show Instantiate Template' as shown below & provide the 'Top level design signals/wires for instantiation inside braces as highlighted, Template my vary depends on PLL configuration.

For IP Catalog,

Regards,

Vicky