Forum Discussion
YigalB1
New Contributor
New ContributorHow to instance SDRAM controller in DE10 Lite?
I am trying to fill the SDTAM chip on the DE10 Lite from Quartus, using a .mif file. From what I read , the SDRAM is DDR4, yet in the IP catalog includes DDR2/DD3/LPDDR2 with UniPhy. Which instance...
- Clearly ease of use. Works without installing JTAG stack (at least Standalone-Programmer) on the client computer.
Altera/Intel RS232 UART IP uses AVMM interface which I don't need in basic HDL debug logic design. I have simple Rx and Tx code with fixed baudrate (921k) written from the scratch. There's no code I can send you as is, I'll check if I can extract something. There are however tons of UART code on the net.
FvM
Super Contributor
Super ContributorI can send old VHDL that I already posted in a forum. It's the ancestor of my present code.
YigalB1New Contributor
New ContributorThank you for the great positive attitude!
However, VHDL is not my thing....
In the meantime I downloaded a Verilog model from GitHub. I compiled and simulated it and already found few bugs because the author probably made it work for a specific baud rate....
I am not sure why the internal seems so complicated to use with no documentation along with e many file it is using.
I was expecting pure Verilog.
I will search for documentation, yet it seems I will take your advise for using ready to go HDL, instead of the UART-RS232 IP.
