how to increase frequency

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Hi all,

I don't see the design is completely pipelined.

all statements involving three additions can be further pipelined e.g.

sum1 <= row1_reg[23:16] + row1_reg[15:8] + row1_reg[7:0];

into :

sum1a <= row1_reg[23:16] + row1_reg[15:8];

sum1b <= row1_reg[7:0];

sum1 <= sum1a + sum1b;

and so on.

Moreover, there is another way of doing the average FIR filter using feedback and subtractor instead of full additions.

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Hi ,

I run a test and it looks like that , as FvM mentioned, the divider is the root cause for the problem.

Kind regards

GPK