--- Quote Start ---
reg [9:0] sum1;
reg [9:0] sum2;
reg [9:0] sum3;
reg [11:0] sum4;
always @ (posedge core_clk or negedge reset_n)
begin
if(!reset_n)
begin
sum1 <= 10'd0;
sum2 <= 10'd0;
sum3 <= 10'd0;
end
else
begin
sum1 <= row1_reg[23:16] + row1_reg[15:8] + row1_reg[7:0];
sum2 <= row2_reg[23:16] + row2_reg[15:8] + row2_reg[7:0];
sum3 <= row3_reg[23:16] + row3_reg[15:8] + row3_reg[7:0];
end
end
always @ (posedge core_clk or negedge reset_n)
begin
if(!reset_n)
sum4 <= 12'd0;
else
sum4 <= sum1 + sum2 + sum3;
end
always @ (posedge core_clk or negedge reset_n)
begin
if(!reset_n)
begin
average <= 12'd0;
avg_valid <= 1'b0;
end
else
begin
average <= (valid_flag_r && red_pulse) ? sum4 / 9 : average;
avg_valid <= ((valid_flag_r && red_pulse) || (valid_flag_g && green_pulse)
|| (valid_flag_b && blue_pulse))? 1'b1 : 1'b0;
end
end
This is basically a part of Average and Median Filter Implementation.
Right now I am working with 16MHz clock and taking my output through RS232 at 38.4 kbps. But say if I have to work with 48MHz clock with 115 kbps RS232 baud rate, my design won't work!!
--- Quote End ---
Hi,
in which always block is the longest path located ?
Kind regards
GPK
Honored Contributor
